EEL 5322 VLSI Circuits and Technology, Fall 2007

 

Professor: William R. Eisenstadt,

Program Assistant: Marcus Moore

Office: 529 NEB

Office: 440 NEB ( morning)

Telephone: (352) 392-4946

Telephone: (352) 392-8422 

Facsimile: (352) 392-8381

Facsimile: (352) 392-0044

E-mail: wre@tec.ufl.edu

Web: http://www.tec.ufl.edu/~wre/

 

 

Class Period and Location:  7th period, 1:55 pm to 2:45 pm, NEB 201

Office Hours:  M, W, F:  12:45 pm to 1:45 pm

TA:  Moishe Groger, 352 392-2725, Office 505 NEB, moishe@groger.net

Required Texts: Richard C. Jaeger, "Introduction to Microelectronic Fabrication," Second Edition, Modular Series on Solid State Devices, Volume 5, Prentice Hall, ISDN 0-201-44494-7, 2002.

Jan. M. Rabaey, A. Chandrakasan, and B.Nikolic, "Digital Integrated Circuits, A Design Perspective," 2nd Edition, Prentice Hall, ISDN 0-13-090996-3, 2003.

Course Goals: To develop proficiency in analyses, design and implementation of CMOS circuits. To develop understanding of interdependence of CMOS circuit design with process technology and IC manufacturing. To be a designer in modern CMOS processes with high level of manufacturing variations.

Computer and Software Required:
Workstations with CADENCE Design system on campus, off-campus can use X-Windows  or X-terminal on a  high-speed internet link to UF Campus Computers, or can use equivalent IC design software. 

All students are required to have a Gator link account and use WebCT/Vista for course handouts, grade information, course notices, etc, see e-learning support services and Vista

Course Study Requirements:
Students are responsible to study all in class materials including those written on the board and presented orally, all Class Handouts all assigned readings, all projects and homework. Absence from class can result in missing materials tested on exams. 

Work Requirements:

Homeworks
Computer Laboratories and projects
Exams: Quizzes, Midterms and Final

Examinations: Quizzes as assigned
Midterm 1: Friday, September. 28, 2007
Midterm 2: Friday, October 26, 2007.
Final: Tuesday, December 11, 2007, 10:00 am to Noon.

 Due to the size of the class these times and dates are firm. Contact me if there is a medical emergency before the examA Doctor's note is required for a midterm or final makeup! Grades will be on a curve and your relative statistical performance to the class grades counts, not your absolute numerical performance. For example, if you have a 95 average and the class median is 98 (not likely) you will get a B.

Preliminary Grading Policy:
Homework and Projects - 15%
Midterms and Quizzes- 55%
Final - 30%

Academic Honesty:
All students admitted to the University of Florida have signed a statement of academic honesty committing themselves to be honest in all academic work and understanding that failure to comply with this commitment will result in disciplinary action.

This statement is a reminder to uphold your obligation as a student at the University of Florida and to be honest in all work submitted and exams taken in this class and all others.

Students requesting classroom accommodation must first register with the Dean of Students Office. The Dean of Students Office will provide documentation to the student who must then provide documentation to the instructor when requesting accommodation.

Course Outline:

Weekly Date, (No. of Classes) Class topics, Readings

08/23 (1) What is VLSI, Statistics Review

Chap. 2 .1, 2.2 and 2.3 of Rabaey,  1.2, 1.3.1 Jaeger, Class handouts

08/27 (3) CMOS X-section,  Intro to Design rules, Ion Implantation,

Chap. 5 .1, 5.2, 5.3, 5.4 of Jaeger

09/05 (2) (Sept.4, 2007 is the Labor Day holiday with no classes) Diffusion,

Chap. 4.1, 4.2, 4.3, 4.4, 4.5, 4.6 of Jaeger

09/10 (3) Oxidation, Film Deposition

Chap. 3.1, 3.2, 3.3, and Chap. 6.1, 6.2, 6.3 of Jaeger

09/17 (3) CMP, Cleaning, Etch, Photo-Lithography

Chap. 7.7, 7.8, 3.8.2 and Chap. 2.1, 2.2, 2.3, 2.4, 2.5 of Jaeger

09/24 (3) Photo-Lithography, Yield, Midterm 1

Chap. 1.3.2 , 9.1, 9.3.5, and Chap. 8.7  of Jaeger

10/1 (3) CMOS Flow, Isolation and Latch-up, Layout Layers and X-sections

Chapter 2.2 Rabaey

10/8 (3) Design Rules, Resistance, Capacitance, MOS Transistors

Chap. 4.1 to 4.3 and Chap. 3.3  of Rabaey and 9.2, 9.3 Jaeger

10/15 (3) MOS Transistors, CMOS Inverters

Chap. 3.3 and Chap. 5 of Rabaey

10/22 (3) CMOS Inverters, Midterm 2

Chap. 5 of Rabaey

10/29 (3) Combination Logic, Compound Gates

Chap. 6 of Rabaey

11/5  (2) Transmission Gates, Memory (Homecoming Holiday, Nov 2, 2007)

Chap. 6 and Chap. 12 of Rabaey

11/14 (3) Memory, Pseudo NMOS, (Veterans' Day Holiday Nov 12, 2007)

Chap. 6 of Rabaey

11/19 (2) Pass Trans. Logic (Thanksgiving Holiday Nov. 21 and Nov. 22, 2007)

Chap. 6 of Rabaey

11/26 (3) Precharge Logic, Dynamic and Domino Logic, Logic Comparison, Noise

Chap.6 of Rabaey

12/2 (2) Testing of CMOS (Study days Dec 6 and Dec 7, 2007)

Appendix. H of Rabaey

12/11/2007, Final Exam Tuesday, December 11, 2007, 10:00 am to Noon.