Differential Pair Circuits

Review

1. Differential Gain
   1. Single Ended = (RD || r_o) * gm / 2
   2. Differential = (RD || r_o) * gm
2. Common Mode Gain
   1. R_C / 2R
3. Common Mode Rejection Ratio

Common Mode Example

1. Matched pair of MOS V_T=1, k=250uA/V², lambda=0.02^-1
2. Supply current equal 250uA, RD = 100k
3. Small Signal Parameters
   1. g_m = sqrt(2 * 250uA * 125uA) = 0.25mS
   2. r_o = 1/ (0.02 * 125uA) = 400k
4. Equivalent Amp
   1. Input resistance infinite
   2. Differential Gain = gm * (RD || ro) = -20
   3. Single Ended Gain = DiffGain / 2 = -10
   4. Output Resistance = 2 * 80k = 160k
5. Common Mode Gain
   1. A_cm = - g_m Rd / (1 + 2 g_m R) = - 0.25mS * 100k / (1 + 2 * 0.25mS * 200k) = -0.25
6. CMRR = -10 / -0.25 = 40

Offset Voltages - Device/Resistor Mismatch

1. Consider the case of mismatched devices/resistors
2. Ground inputs
3. Because of the mismatch, output mismatch occurs - V_O
4. Referenced back to the input
5. Input offset voltage - V_OS = V_O / A_d
6. Consider a resistor mismatch
7. R_C1 = R_C + dR_C/2, R_C2 = R_C + dR_C/2
8. V_C1 = V_CC - I/2 * R_C1 = V_CC - I/2 * (R_C + dR_C/2)
9. V_O = V_C2 - V_C1 = I/2 dR_C
10. Example
    1. Use 1% resistors (10k), 1mA bias current in BJT diff pair
    2. Differential Gain = 10k * 20mS = -200V/V
    3. V_O = 0.5mA * 100 = 50mV
    4. V_OS = 50mV / 200V/V = 0.25mV
11. Other mismatches can also be analyzed - see 6.5

Active Load - MOS

1. PMOS Current Mirror as load - diode connected PMOS on one side
2. Diode side analysis
   1. NMOS M1 has current g_m vd/2 flowing
   2. PMOS M3 has to source that current - gate voltage changes to do so...
3. Output side analysis
   1. NMOS M2 has current - g_m vd/2 flowing
   2. PMOS M4 mirrors PMOS M3 current g_m vd/2 flowing
4. Both output currents must flow into output resistance of amplifier
5. Rout = r_op || r_on
6. Gain = A_d = g_m * (r_op || r_on)
7. Input resistance is infinite

MOS Active Load Example

1. Matched pair of NMOS V_T=1, k=250uA/V², lambda=0.02^-1
2. Note - PMOS generally would have to be wider...
3. Current Mirror Analysis
   1. 8k with NMOS diode connected
   2. 5V = k/2 * 4k * (V_GS-V_T)² + V_GS
   3. I_DS = 0.5mA
   4. R = 1 / (0.02 * 0.5mA) = 100k
4. Input Resistance = infinite
5. Output Resistance
   1. Rout = r_op || r_on = 0.5 / (0.02 * 0.25mA) = 100k
6. Gain
   1. A_d = g_m * (r_op || r_on) = sqrt(2 * 0.25 * 0.25) * 100k = 35.3V/V
7. Common Mode Gain
   1. A_cm = - g_m Rout / (1 + 2 g_m R) = Rout / 2R = 100k / 200k = 0.5
8. CMRR
   1. A_d / A_cm = 35.3 / 0.5 = 70

Bipolar Current Mirrors

1. Diode connected bipolar
2. Collector and base at same voltage - forward active
3. Base at 0.7V
4. Reference current splits into collector and base
5. Mirror base / emitter circuit into matching bipolar
6. Remember I_C = I_S exp( V_BE / V_t )
7. Base emitter voltages identical
8. Base draws current, however
9. I_C = I_ref * ß / (ß + 2)
10. MOS can mirror infinitely, bipolar draws current which limits maximum

Active Load - Bipolar

1. PNP Current Mirror as load - diode connected PNP on one side
2. Diode side analysis
   1. NPN Q1 has current g_m vd/2 flowing
   2. PNP Q3 has to source that current - base voltage changes to do so...
3. Output side analysis
   1. NPN Q2 has current - g_m vd/2 flowing
   2. PNP Q4 mirrors PMOS Q3 current g_m vd/2 flowing
4. Both output currents must flow into output resistance of amplifier
5. Rout = r_op || r_on
6. Gain = A_d = g_m * (r_op || r_on)
7. Input resistance is 2 r_pi

Conclusions

• Offset Voltages
• Active Loads

Next Time

• More Active Load
• Cascode